CodeGen.hpp

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#pragma once
#include "../AST/AST.hpp"
#include "../Runtime/Value.hpp"
#include <cstdint>
#include <map>
#include <string>
#include <vector>
 
namespace Phasor
{
enum class OpCode : uint8_t
{
    // Stack operations
    PUSH_CONST, 
    POP,        
 
    // Arithmetic operations
    IADD,       
    ISUBTRACT,  
    IMULTIPLY,  
    IDIVIDE,    
    IMODULO,    
    FLADD,      
    FLSUBTRACT, 
    FLMULTIPLY, 
    FLDIVIDE,   
    FLMODULO,   
    SQRT,       
    POW,        
    LOG,        
    EXP,        
    SIN,        
    COS,        
    TAN,        
 
    // Unary operations
    NEGATE, 
    NOT,    
 
    // Logical operations
    IAND,  
    IOR,   
    FLAND, 
    FLOR,  
 
    // Comparison operations
    IEQUAL,          
    INOT_EQUAL,      
    ILESS_THAN,      
    IGREATER_THAN,   
    ILESS_EQUAL,     
    IGREATER_EQUAL,  
    FLEQUAL,         
    FLNOT_EQUAL,     
    FLLESS_THAN,     
    FLGREATER_THAN,  
    FLLESS_EQUAL,    
    FLGREATER_EQUAL, 
 
    // Control flow
    JUMP,          
    JUMP_IF_FALSE, 
    JUMP_IF_TRUE,  
    JUMP_BACK,     
 
    // Variable operations
    STORE_VAR, 
    LOAD_VAR,  
 
    // I/O and control
    PRINT,       
    PRINTERROR,  
    READLINE,    
    IMPORT,      
    HALT,        
    CALL_NATIVE, 
    CALL,        
    SYSTEM,      
    SYSTEM_OUT,  
    SYSTEM_ERR,  
    RETURN,      
 
    // Literal values
    TRUE_P,   
    FALSE_P,  
    NULL_VAL, 
 
    // String operatoins
    LEN,     
    CHAR_AT, 
    SUBSTR,  
 
    NEW_STRUCT, 
    GET_FIELD,  
    SET_FIELD,  
 
    NEW_STRUCT_INSTANCE_STATIC, 
    GET_FIELD_STATIC,           
    SET_FIELD_STATIC,           
 
    // Register-based operations (v2.0)
    // Data movement
    MOV,          
    LOAD_CONST_R, 
    LOAD_VAR_R,   
    STORE_VAR_R,  
    PUSH_R,       
    PUSH2_R,      
    POP_R,        
    POP2_R,       
 
    // Register arithmetic (3-address code)
    IADD_R,  
    ISUB_R,  
    IMUL_R,  
    IDIV_R,  
    IMOD_R,  
    FLADD_R, 
    FLSUB_R, 
    FLMUL_R, 
    FLDIV_R, 
    FLMOD_R, 
    SQRT_R,  
    POW_R,   
    LOG_R,   
    EXP_R,   
    SIN_R,   
    COS_R,   
    TAN_R,   
 
    // Register comparisons
    IAND_R,  
    IOR_R,   
    IEQ_R,   
    INE_R,   
    ILT_R,   
    IGT_R,   
    ILE_R,   
    IGE_R,   
    FLAND_R, 
    FLOR_R,  
    FLEQ_R,  
    FLNE_R,  
    FLLT_R,  
    FLGT_R,  
    FLLE_R,  
    FLGE_R,  
 
    // Register unary operations
    NEG_R, 
    NOT_R, 
 
    // Register I/O
    PRINT_R,      
    PRINTERROR_R, 
    READLINE_R,   
    SYSTEM_R,     
    SYSTEM_OUT_R, 
    SYSTEM_ERR_R 
};

struct Instruction
{
    OpCode  op;       
    int32_t operand1; 
    int32_t operand2; 
    int32_t operand3; 
    int32_t operand4; 
    int32_t operand5; 
 
    // Default constructor
    Instruction() : op(OpCode::HALT), operand1(0), operand2(0), operand3(0), operand4(0), operand5(0)
    {
    }
 
    // Full constructor
    Instruction(OpCode op, int32_t op1 = 0, int32_t op2 = 0, int32_t op3 = 0, int32_t op4 = 0, int32_t op5 = 0)
        : op(op), operand1(op1), operand2(op2), operand3(op3), operand4(op4), operand5(op5)
    {
    }
};

struct StructInfo
{
    std::string              name;            
    int                      firstConstIndex; 
    int                      fieldCount;      
    std::vector<std::string> fieldNames;      
};

struct Bytecode
{
    std::vector<Instruction>   instructions;     
    std::vector<Value>         constants;        
    std::map<std::string, int> variables;        
    std::map<std::string, int> functionEntries;  
    int                        nextVarIndex = 0; 
 
    // Struct section (planned usage by future struct codegen)
    std::vector<StructInfo>    structs;       
    std::map<std::string, int> structEntries; 

    int addConstant(const Value &value)
    {
        constants.push_back(value);
        return static_cast<int>(constants.size()) - 1;
    }

    int getOrCreateVar(const std::string &name)
    {
        auto it = variables.find(name);
        if (it != variables.end())
        {
            return it->second;
        }
        int index = nextVarIndex++;
        variables[name] = index;
        return index;
    }

    void emit(OpCode op, int32_t op1 = 0, int32_t op2 = 0, int32_t op3 = 0, int32_t op4 = 0, int32_t op5 = 0)
    {
        instructions.push_back(Instruction(op, op1, op2, op3, op4, op5));
    }
};

class CodeGenerator
{
  public:
    Bytecode generate(const AST::Program &program, const std::map<std::string, int> &existingVars = {}, int nextVarIdx = 0,
                      bool replMode = false);
 
  private:
    Bytecode bytecode;       
    bool     isRepl = false; 
    // Inferred types for variables (simple, flow-insensitive mapping)
    std::map<std::string, ValueType> inferredTypes;
 
    // Register allocation for v2.0
    uint8_t           nextRegister = 0; 
    std::vector<bool> registerInUse;    

    uint8_t allocateRegister()
    {
        for (size_t i = 0; i < 256; i++)
        {
            if (i >= registerInUse.size())
            {
                registerInUse.resize(i + 1, false);
            }
            if (!registerInUse[i])
            {
                registerInUse[i] = true;
                return static_cast<uint8_t>(i);
            }
        }
        throw std::runtime_error("Out of registers");
    }

    void freeRegister(uint8_t reg)
    {
        if (reg < registerInUse.size())
        {
            registerInUse[reg] = false;
        }
    }

    void resetRegisters()
    {
        registerInUse.clear();
        nextRegister = 0;
    }

    bool isLiteralExpression(const AST::Expression *expr, Value &outValue);

    ValueType inferExpressionType(const AST::Expression *expr, bool &known);
 
    void generateStatement(const AST::Statement *stmt);              
    void generateExpression(const AST::Expression *expr);            
    void generateVarDecl(const AST::VarDecl *varDecl);               
    void generateExpressionStmt(const AST::ExpressionStmt *exprStmt); 
    void generatePrintStmt(const AST::PrintStmt *printStmt);          
    void generateImportStmt(const AST::ImportStmt *importStmt);       
    void generateExportStmt(const AST::ExportStmt *exportStmt);       
    void generateNumberExpr(const AST::NumberExpr *numExpr);          
    void generateStringExpr(const AST::StringExpr *strExpr);          
    void generateIdentifierExpr(const AST::IdentifierExpr *identExpr); 
    void generateUnaryExpr(const AST::UnaryExpr *unaryExpr);           
    void generateCallExpr(const AST::CallExpr *callExpr);              
    void generateBinaryExpr(const AST::BinaryExpr *binExpr);           
    void generateBlockStmt(const AST::BlockStmt *blockStmt);           
    void generateIfStmt(const AST::IfStmt *ifStmt);                    
    void generateWhileStmt(const AST::WhileStmt *whileStmt);           
    void generateForStmt(const AST::ForStmt *forStmt);                 
    void generateReturnStmt(const AST::ReturnStmt *returnStmt);        
    void generateUnsafeBlockStmt(
        const AST::UnsafeBlockStmt *unsafeStmt);                     
    void generateFunctionDecl(const AST::FunctionDecl *funcDecl);    
    void generateBooleanExpr(const AST::BooleanExpr *boolExpr);      
    void generateNullExpr(const AST::NullExpr *nullExpr);            
    void generateAssignmentExpr(const AST::AssignmentExpr *assignExpr);   
    void generateStructDecl(const AST::StructDecl *decl);
    void generateStructInstanceExpr(const AST::StructInstanceExpr *expr);
    void generateFieldAccessExpr(const AST::FieldAccessExpr *expr);
    void generatePostfixExpr(const AST::PostfixExpr *expr);
    void generateBreakStmt();
    void generateContinueStmt();
    void generateSwitchStmt(const AST::SwitchStmt *switchStmt);
 
    // Loop context for break/continue
    std::vector<int>              loopStartStack;     // Stack of loop start positions
    std::vector<std::vector<int>> breakJumpsStack;    // Stack of break jump positions to patch
    std::vector<std::vector<int>> continueJumpsStack; // Stack of continue jump positions to patch
};
 
} // namespace Phasor